1. Field of the Invention
The present invention relates to semiconductor integrated circuit structures and methods of making such structures and, more particularly, to a method of making and structure of SRAM cells.
2. Discussion of the Related Art
CMOS static random access memories (SRAM) are used in the semiconductor and computer industries as a result of the combination of speed, low power, and no requirement for refresh. Information can be written into and read out of an SRAM cell faster than with a DRAM cell, because the transistors of the SRAM cell can be switched faster than capacitors can be charged and drained. However, a disadvantage of prior art SRAM cells is that such cells have required a larger footprint to achieve greater speed and stability than DRAM cells.
As semiconductor devices become smaller, it becomes necessary to arrange individual components within a device such that minimal separation distances are achieved. The need to design compact component arrangements occurs most significantly in memory devices. Because of the large number of components needed to fabricate a typical dynamic-random-access-memory (DRAM) or static-random-access-memory (SRAM), the components must be arranged compactly if the overall device dimensions are not to become excessively large. This problem is especially critical in SRAM devices where a typical individual memory cell contains as many as six separate components.
One technique to reduce SRAM memory cell dimensions is to split the wordline over the cell. The wordline controls read and write functions to the cell by turning the access transistors on and off. By splitting the wordline into two separate lines, a more symmetrical cell layout is possible. However, even with a split wordline memory cell design, a need remains to further reduce the overall cell dimensions. Although split wordline designs reduce the area of the cell, fundamental manufacturing limitations remain. Active surface regions of the cell must be made available for the interconnection leads providing supply and ground voltages to the cell. In addition, active surface area must be available for the formation of transistors providing read and write functions for the cell. However, downsizing of components can only be pursued to the limit of the line-width definition capability of the manufacturing process.
Another technique for fabricating a memory cell having a small surface area is to stack MOS transistors in a vertical arrangement. Typically, a driver transistor is formed in the substrate having source, drain, and channel regions in the substrate and a gate electrode overlaying the substrate surface. Then, a load transistor is formed in a thin-film layer overlying the first transistor. By adding an additional electrical component to the device, the thin-film transistor increases the functional capacity of a device while not consuming additional surface area, or requiring further downsizing of components.
While stacking transistors in a vertical arrangement can reduce the surface area of a memory cell, valuable surface area must still be allocated for coupling electrical signals to the memory cell. The electrical signals are typically introduced by metal leads overlying the cell. As the overall area dimensions of the cell decrease, the metal leads carrying electrical signals to and from the cell must be brought closer together. Constructing a cell with stacked transistors can aggravate this problem because elaborate contact interconnection schemes are typically required in a stacked transistor memory cell. Therefore, new cell designs and process methodology must be employed if further reduction in memory cell area is to be achieved while avoiding performance degradation of the memory cell.
The basic SRAM cell can be formed using cross-coupled CMOS inverters having two N channel transistors and two P channel transistors. Typically, the cell is accessed by two N channel control gates for a standard SRAM cell and four control gates for two port memory devices. To conserve physical layout space, the P-channel transistors are often replaced with resistive loads.
Use of the P-channel transistors as the load for the SRAM cell, however, results in the cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the P-channel transistors provide a higher drive current than high resistance devices. Also, use of P-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating P-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs.
A disadvantage of using polycrystalline P-channel load transistors arises where ohmic contact is required between the interconnection of P-channel and N-channel transistors. Ohmic contact between interconnect layers is desirable because no PN junction is formed. A P-N junction is formed, however, where polycrystalline interconnect lines having different conductivity types make contact. A similar junction can be formed when polycrystalline silicon lines having the same conductivity type, but very different doping levels (such as N- to N+) make contact.
The P channel MOSFET device provides a low OFF current and a high ON current to sustain leakage of the storage node. However, if the pulldown transistors exhibit high leakage, the Vcc must be electrically disconnected to reduce the standby current. Additionally, for the P channel device, the cell area is much larger than for the other devices described above. Such a cell and the method of making same are taught in U.S. Pat. No. 5,187,114.
There is thus a need for new SRAM cell design and process methodology if further reduction in memory cell area is to be achieved while avoiding performance degradation of the memory cell.